The use of electrically erasable, programmable read-only memory (EEPROM) devices with floating-gate transistors is well-established. In these devices, each bit is represented by a field-effect transistor (FET) in which a polysilicon floating gate is surrounded by oxide layers which isolate it from both a polysilicon control gate and the substrate. The floating gate may carry a charge to indicate a programmed (logic 1) state, while the absence of a charge indicates an erased (logic 0) state. In the programmed state, the threshold voltage of the FET is higher than in the erased state. This provides a means for detecting the state of a bit or cell.
In some EEPROMs, known as flash EEPROMS, cells may be electrically erased simultaneously in large blocks. One of the problems arising in flash EEPROMs is over-erasure of cells. An over-erased cell has a floating gate with a positive charge, causing the channel under the floating gate to be conductive even with no voltage applied to the control gate. This causes a leakage current which can interfere with the accurate reading of other cells in its column of parallel-connected cells.
One method to prevent over-erasure is to erase the cells with the application of light erasing pulses in steps, checking after each step to determine whether all of the cells have been erased. However, while this method ensures that the threshold voltages of all of the cells will be brought below a certain value, it does not necessarily result in the cells having identical threshold voltages. Instead, because of the variation in the physical characteristics of the cells, a distribution of threshold voltages around a central value results. This distribution may resemble a normal distribution. To achieve uniformity throughout the EEPROM, it is desirable to tighten or compact this distribution, to bring each threshold voltage as close as possible to a central value.
Another problem arising in flash EEPROMs is the limited number of programming-and-erasure cycles to which the cells can be subjected. When a program step is performed for a selected cell after a flash-erase of the array, a high bias voltage on the bitline for the selected cell will cause any other cells with low threshold voltages in the same column as the selected cell to conduct a leakage current. Because of short-channel effects and potential coupling between the bitline and the floating gate, this leakage may occur even if the cells in the same column as the selected cell have positive threshold voltages.
As a result of the leakage current during programming, electrons bombard the high-voltage drain-channel junction, releasing electron-hole pairs underneath the oxide layer that separates the floating gate from the channel. These electron-hole pairs become trapped in the oxide layer, generating interface states or traps and oxide charge. The oxide layer then interacts with the substrate and behaves like a capacitor, shielding the floating gate from the channel. These phenomena cause a gradual degradation in the transconductance of a cell. With reduced transconductance, the cell fails to conduct the expected level of current when turned on, resulting in inaccurate reading of the cell's bit value and, consequently, chip failure.